The invention relates to test circuits and methods in integrated circuits (ICs). More particularly, the invention relates to circuits and methods for determining the effects of high stress currents on conducting layers, contacts, and vias in ICs.
Integrated circuits (ICs) typically include numerous elements that are fabricated on silicon wafers. During the fabrication process, a xe2x80x9csandwichxe2x80x9d of various conducting and non-conducting layers is laid down on a silicon wafer substrate. The conducting layers typically include layers of diffusion (wherein a chemical substance is diffused into the silicon substrate) and polysilicon, as well as several metal layers. The conducting layers are isolated from each other using intermediate layers of non-conducting material (e.g., silicon-dioxide), and electrically connected to one another by way of openings in these isolating layers. By convention, these openings are called xe2x80x9ccontactsxe2x80x9d when the connection is between a diffusion layer or a polysilicon layer and the bottommost metal layer, and xe2x80x9cviasxe2x80x9d when the connection is between two different metal layers.
During the fabrication process, various types of manufacturing defects can occur. For example, a xe2x80x9cshortxe2x80x9d (a short circuit) can appear between two layers of the same type. A short is an inadvertent electrical connection between two constructs. A metal short can occur, for example, when excess metal is laid down during processing such that each metal structure is slightly larger than it is intended to be. Because there are great advantages to using the smallest possible structures in designing an IC, wafer fabrication plants typically push the envelope by defining minimum separations that are the smallest feasible. Therefore, shorts are a common type of defect in integrated circuits.
Another type of defect commonly found in ICs is an xe2x80x9copenxe2x80x9d (an open circuit). An open is an inadvertent disconnect between two points designed to be electrically connected. A metal open can occur, for example, when insufficient metal is deposited in a particular location along a narrow metal line. In this case, a portion of the narrow metal line can effectively disappear from an IC and little or no current is conducted along that portion of the metal line.
An open can also occur in a via or contact (i.e., an opening in the non-conducting layer), when, for example, the contact or via etch is insufficiently deep to reach the underlying conducting layer. Also common are xe2x80x9cpartial opensxe2x80x9d or resistive contacts and vias, where only a very small area contacts the underlying conducting layer or some degradation of the conducting material in the contact or via has occurred. Resistive contacts and vias not only affect the circuit speed and functionality, but are also considered unreliable, because they tend to become more open (more resistive) after the application of high currents.
Methods have been devised to test the processing of a silicon wafer by including a xe2x80x9ctest chipxe2x80x9d at various points on the wafer. The test chip (also called a xe2x80x9cDefect Monitor Vehiclexe2x80x9d, or DMV) includes structures intended for the purpose of testing for shorts and opens. If shorts and opens are found when testing the DMV, it is logical to assume that similar defects will be found in the other ICs on the wafer. Because the DMV is quick and easy to test, valuable test time is saved by discarding wafers that include high numbers of shorts and opens in the DMVs. Additionally, the DMVs can be used to track down problem areas in the fabrication process.
Voogel describes one such Defect Monitor Vehicle in U.S. Pat. No. 6,281,696 B1, which is incorporated herein by reference. Voogel""s DMV contains a core array that includes interleaved xe2x80x9cforkxe2x80x9d structures for detecting shorts and serpentine structures for detecting opens in diffusion, polysilicon, and metal layers. Voogel also shows and describes switches, decoders, and control circuitry for selectively testing each of these elements within the core array.
Voogel""s test structure is useful in detecting and locating shorts and opens generated during the IC fabrication process. However, Voogel""s test structure does not detect resistive contacts and vias, because the effect of a single resistive point in an array is often too small to be noticed. Also, it is not possible to send large currents through the resistive chains in Voogel""s array, because the total resistance of the chain is too high. To apply a large current to the chain would require a voltage far exceeding what the control transistors can handle.
Therefore, to test for resistive contacts and vias requires an improvement to the accuracy of measuring the resistance of a resistive chain (e.g., the metal line or contact or via chain). Preferably, the resistance measurement should be accurate to within a few percentage points. Any structure that has more than a few percentage points of change in resistance value (i.e., enough change to be measured accurately) probably contains at least one resistive contact or via that has changed in value.
It is also desirable to allow for higher current stresses of the resistive structures in order to monitor the effect of the higher currents on the structures.
Any high speed switching circuitry within an IC has metal lines, contacts, and vias that conduct large amounts of current for a short time. For example, when the input signal driving an inverter changes state, both the N and P channel transistors in the inverter are momentarily on at the same time, causing a xe2x80x9ccrossbar currentxe2x80x9d. Also, there is a high current flow through one of the N and P channel transistors as the capacitive load of the inverter is charged. These high current stresses can change the resistance of the conducting layers in an IC, which can adversely affect the timing and even the functionality of the IC. The high current stresses can also reshape the structures forming the IC circuits, causing additional shorts and opens that were not present after wafer fabrication.
Therefore, it is desirable to provide structures and methods for detecting and locating changes in resistance and/or shorts in ICs that have been subjected to high current stress.
The invention provides a Reliability Monitor Vehicle (RMV), a test chip that is included in an IC wafer for the purpose of testing the reliability of ICs on the wafer under high current stress. The RMV and the related methods of the invention provide a vehicle both for debugging a semiconductor fabrication process and for predicting the behavior under stress of other ICs on the same wafer.
According to a first embodiment of the invention, an IC test circuit is provided that includes two stress input terminals, two sense terminals, two sensing transistors, a select transistor, and a resistor. The two ends of the resistor are coupled to the two sense terminals through the two sensing transistors. One end of the resistor is also coupled to one of the stress input terminals; the other end of the resistor is coupled to the other stress input terminal through the select transistor. When the test circuit is selected, the sensing and select transistors are turned on. A current path is formed between the two stress input terminals, and the voltage differential can be measured across the resistor using the two sense terminals.
The term xe2x80x9cresistorxe2x80x9d as used herein means a structure in an IC having a measurable resistance. A resistor can be, for example, a conductive line in a single fabrication layer, such as a long metal line, or a combination of several different fabrication layers. For example, a resistor can include a contact or via chain, e.g., a chain of same layer contacts or vias connecting two alternating metal lines.
In one embodiment, the test circuit is a system that includes a current source for applying either a low non-stressing current or a high stress current between the two stress input terminals. Also included in the system is a voltage meter coupled to the two sense terminals that can be used to measure the voltage across the resistor. The resistance value of the resistor before, during, and/or after stress is applied can easily be derived from the applied currents and measured voltages.
Some embodiments of the invention provide additional resistors coupled between the stress terminals and the sense terminals. The additional resistors can be, for example, of different fabrication layers, or the same fabrication layer but with different dimensions (e.g., width, length, spacing, or overlapping of vias or contacts).
Another embodiment includes one or two additional resistors paralleling the first resistor and manufactured from the same fabrication layer. These additional resistors are used to test for short circuit conditions after application of the high stress current.
Another aspect of the invention provides a system for testing reliability in an IC. The system includes a core cell array of test circuits, row and column select circuits, global stress lines, and global sense lines. A first set of column switches is coupled between the core cell array and the global stress lines, which are used to supply a high stress current to a selected column of test circuits in the core cell array. All selected rows in the selected column receive the high stress current. A second set of column switches is coupled between the core cell array and the global sense lines, which are used to test the resistance through a selected test circuit before and after application of the high stress current. Again, the row select circuit determines which test circuit in the selected column is measured.
Other embodiments include local stress and sense lines coupled to each column of test circuits in the core cell array, and/or a short detector circuit. In some embodiments, the row and column select circuits are implemented using decoders. In other embodiments, one or both of the row and column select circuits are implemented as shift registers that cycle sequentially through each row or column in the array.
Another aspect of the invention provides a method of testing reliability in an IC including an array of test circuits, each test circuit including a resistor. The method includes selecting a first test circuit from the array, measuring a pre-stress resistance value for the resistor in the selected test circuit, applying a high stress current across the resistor, removing the high stress current, and measuring a post-stress resistance value for the resistor.
Other embodiments include measuring additional resistance values before applying and after removing the high stress current. For example, a pre-stress resistance value can be measured for each of several test circuits by selecting each test circuit in turn, applying a current through the resistor of the selected test circuit, and measuring a pre-stress voltage differential between the two sense terminals of the selected test circuit. Then, each test circuit can be selected and stressed by applying a high stress current across the resistor. Finally, each test circuit can be selected and a post-stress resistance value can be measured for each test circuit.
One embodiment includes applying,a positive voltage to one stress input terminal, and then testing a short sensing terminal for the positive voltage, both before and after applying the high stress current. These steps test for whether or not the high stress current has created a short in the test circuit. It is not necessary to test separately for opens through the resistor after applying the high stress current. Measuring the post-stress resistance will detect any open circuits in the resistor by returning an infinite resistance value.